IBM and Siemens are collaborating to prepare engineers for 0.7 nm chip design using the new 3D Nanostack architecture, with a pilot design kit expected in early 2027.
Huawei's Chief Scientist for EDA, Huang Yu, stated that EDA tools present the greatest challenge to the company's Tau law framework during the 2026 Bay Area Chip Exhibition.
Empyrean Technology reports that domestic EDA tool coverage in China has risen to 85 percent, with plans to reach 80 percent coverage for major process nodes by the end of the year.
Synopsys plans to integrate local AI models into its chip design tools for the Chinese market to bypass regional restrictions while maintaining compliance with US export laws.
Synopsys has announced a strategic partnership with OpenAI to develop the GPT-Synopsys AI model, while dismissing unconfirmed reports regarding collaborations with Chinese AI labs.
OpenAI and Synopsys are partnering to build GPT-Synopsys, an AI model designed to autonomously operate EDA tools and accelerate the chip design process.
Synopsys and OpenAI have signed a multi-year agreement to develop the GPT-Synopsys model, which uses AI agents to automate semiconductor design workflows.
Reports of a new OpenAI and Synopsys chip design tool remain unverified as neither company has confirmed the product.
AI is shifting from a simple optimization tool to an active participant in semiconductor development, automating RTL generation, verification, and architectural exploration for next-gen chips.
Empyrean Technology has integrated AI agents into its chip design process, reducing layout time by four times and shifting to a token-based business model.
