The Kirin 9050 Pro processor features the LogicFolding technology, which enables the vertical stacking of active silicon layers. This architecture allows for increased component density without requiring a transition to a more advanced manufacturing process.
The processor consists of two stacked dies, each measuring approximately 11.13 by 10.84 millimeters, totaling 120.65 square millimeters per layer. The first die houses the primary computing logic, while the second contains SRAM and cache memory, connected by high-density vertical interconnects.
Huawei and SMIC reportedly utilize different manufacturing nodes for the stack. The computing die is produced using the SMIC N+3 process, while the memory die uses the N+2 process. This vertical integration aims to reduce data latency by shortening the physical distance between components.
While smaller individual dies can improve production yields by minimizing the impact of defects, the complex vertical assembly process may lower the overall output of functional chips. Currently, Huawei limits the use of the Kirin 9050 Pro to its flagship Pro Max and RS smartphone models.
