The Architect Labs Platform has autonomously designed the Redwood AI accelerator, moving from a text-based technical specification to a functional FPGA prototype in under two weeks. The system handled performance modeling, digital circuit description, testing, verification, and firmware generation. Subsequent specification changes allowed for new FPGA versions within 48 hours.
The Redwood architecture utilizes a tile-based design to minimize latency and power consumption by keeping data near compute units. Each block operates independently, with global timing managing execution. Developers report 95% code and functional coverage, with the initial RTL version functioning without errors upon deployment to the FPGA.
In tests using the Qwen3 0.6B model, the Redwood Nano on FPGA achieved 12.1 tokens per second at 250 MHz. Researchers project that a future version on an 8 nm Samsung process will reach 49 tokens per second at 1.335 watts, compared to 2.59 watts for the Nvidia Jetson Orin Nano. These figures represent a projected 1.75x performance lead and 3.4x efficiency advantage.
Architect Labs also conducted a recursive self-improvement experiment, using an instance of the Qwen3 model running on Redwood to identify optimizations for its own operations. The system successfully discovered improvements for timing characteristics and core logic, though the developers noted this remains a limited form of autonomous enhancement.
The company is currently preparing for physical production, with plans to manufacture the chip using a TSMC process. This next phase aims to validate whether the calculated performance metrics hold true on silicon. The project intends to demonstrate that hardware development cycles can be reduced from years to weeks through this automated approach.
