TSMC has announced a breakthrough in SRAM cell scaling, ending an eight-year period of stagnation. Starting with the N5 process in 2020, the area occupied by SRAM cells remained at 0.021 square micrometers throughout the N3 and N2 generations.
The upcoming A14 process, scheduled for mass production in 2028, is expected to reduce the SRAM cell area to less than 0.017 square micrometers. This represents a scaling improvement of more than 19 percent compared to the N5 process.
This advancement allows for larger cache capacities on future chips or the reallocation of silicon space for other functional blocks. The A14 process also promises a 20 percent increase in transistor density compared to N2.
Performance metrics for the A14 technology include a 10 to 15 percent increase in switching speeds or a 30 percent reduction in power consumption at the same performance level. TSMC also plans to introduce new integration technologies.
In terms of competition, TSMC's A14 process aims to outperform Intel's 18A technology, which currently maintains an SRAM cell area of 0.021 square micrometers. Samsung Electronics has not publicly disclosed similar data for its processes.
