Chinese semiconductor manufacturers are increasingly relying on deep ultraviolet (DUV) lithography and multiple patterning techniques to produce advanced chips, as access to extreme ultraviolet (EUV) systems remains restricted. While this approach allows for the creation of 7nm-class and near-5nm-class processors, it introduces significant economic and technical trade-offs compared to EUV-based manufacturing.
The primary challenge with multiple patterning is the accumulation of process variations and alignment errors, which often lead to higher defect rates and lower yields. To maintain reliability, manufacturers must increase the physical size of the chip dies, which reduces the number of usable dies per wafer and drives up production costs. Analysts note that EUV becomes more cost-effective than DUV once a process requires four or more masks.
Data from Morgan Stanley indicates that the Chinese DRAM manufacturer CXMT produces roughly one-third the number of bits per wafer compared to Western competitors. Despite these inefficiencies, projections suggest that China could increase its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 by expanding production capacity. Similarly, AI chip self-sufficiency is expected to rise from 42% in 2025 to 70% by 2030.
Experts, including CTO of Fractilia Chris Mack, emphasize that while DUV can be pushed to its limits, it is unlikely to be economically viable for 3nm or 2nm nodes. Manufacturers opting for DUV must accept larger dies, lower yields, and longer production times. While Micron successfully utilized DUV for its 1-alpha DRAM generation, the company eventually transitioned to EUV for its 1-gamma process to achieve higher bit density.
