Tesla has updated its hardware roadmap, rebranding its inference accelerators from AI to SI. The upcoming SI5 processor, expected to use 3nm and 2nm process technologies from TSMC and Samsung, will feature a multi-chip module design and 96 GB of memory. It aims for a 40-fold performance increase over the current HW4 generation.
The sixth-generation SI6 accelerator is scheduled for release between 2029 and 2030. Tesla has secured a manufacturing agreement with Samsung Foundry to produce these chips using a 2nm-class process through 2033. The SI6 is projected to offer 80 times the compute performance and eight times the memory capacity of the HW4.
Tesla is also reviving its Dojo training accelerator project with the third-generation D3. Unlike the previous wafer-scale D1 and D2 models, D3 will utilize a chiplet-based architecture with 2.5D and 3D packaging and stacked HBM. The company intends to optimize this hardware for scaling and potential extraterrestrial deployment.
