Nagare Labs is developing Z2RAM, a capacitorless memory technology designed to combine the speed of SRAM with the density of DRAM. The architecture utilizes two transistors and a shield, aiming for energy consumption well under a picojoule per bit. The company plans to build the memory by depositing layers directly onto an accelerator die, potentially reaching over 100 layers using standard 300 mm DUV lithography tools without the need for EUV.
Recent testing of a three-transistor boosted cell showed data retention exceeding 300 seconds at 85 degrees Celsius. While the technology is currently in the lab prototype stage, Nagare Labs projects a cell size of 0.0168 square micrometers at the 7nm process node. The company is exploring the potential for 5.7x higher bit density compared to standard 7nm SRAM, though these figures remain based on simulations and lab measurements.
The startup is currently seeking R&D fabrication partners to scale production beyond university clean rooms. Nagare Labs aims to provide sampling of Z2RAM tiles within four years, with potential production shipments targeted within the next decade. The company faces challenges regarding integration standards and long-term reliability, as it currently lacks its own manufacturing facilities.
Nagare Labs recently secured $5 million in funding led by Playground Global. Pat Gelsinger, who serves as a general partner at Playground Global, has joined the company's board of directors. The development follows previous industry attempts at capacitorless memory, such as the Z-RAM technology licensed by AMD two decades ago.
