During the 2026 technical webinar, Micron announced that it is moving away from 4F² DRAM architecture. The company cited high complexity and prohibitive costs as the primary reasons for abandoning this path after two decades of research. Instead, Micron is shifting its focus toward 3D DRAM technology to overcome the scaling limitations inherent in traditional 2D 6F² designs.
Micron is currently scaling its 7th generation 10nm-class node, 1δ, which is expected to provide a 25% increase in memory density while optimizing production costs. This node will be integrated into a wide range of products, including HBM5, vHBM, vEIM, LPDDR, and DDR. The company also plans to transition DRAM CMOS logic circuits to a 3D architecture to enhance overall performance.
The company's roadmap includes the 8th generation 10nm-class node, 1ε, which will utilize wafer bonding technology. Furthermore, development has begun on the 1st generation sub-10nm node, designated as ζÅ, which will incorporate High NA EUV lithography. For the 2nd generation sub-10nm node, known as ηÅ, Micron is currently exploring the application of new materials.
