High-NA EUV lithography offers 8nm resolution compared to 13nm for Low-NA systems. However, its anamorphic optics limit the exposure field to 26x16.5 mm with standard 6x6-inch masks. This forces manufacturers to use stitching for larger chips, which reduces throughput on ASML Twinscan EXE:5200B scanners from 175 to 125 wafers per hour.
To solve this, the industry is evaluating 6x12-inch photomasks to restore the 26x33 mm full exposure field. This transition requires a complete overhaul of the manufacturing infrastructure, including mask-blank production, inspection systems, and ASML scanner designs. Suppliers like AGC and Hoya would need to adapt equipment for larger substrates.
Intel, Samsung, and TSMC are collaborating with ASML on this initiative. Intel has been working on the format for three years. TSMC plans to launch a 6x12-inch pilot line by 2031, aiming for full readiness by 2033. Samsung intends to adopt High-NA EUV for DRAM production by 2028, initially using standard 6x6-inch masks.
The 6x6-inch and 6x12-inch formats will likely coexist, as the smaller masks remain sufficient for most client processors. Larger masks will be reserved for high-end components like AI accelerators, data center CPUs, and GPUs where stitching is impractical. The transition is expected to take years due to the complexity and costs involved.
