Axera has officially introduced its new M9 series of 5nm intelligent driving chips, consisting of the flagship M97 and the mainstream M95 models. Both processors are designed to meet AEC-Q100 automotive standards and feature an ASIL-D safety island, with the overall chip architecture achieving ASIL-B compliance. The hardware also supports redundant configurations using two chips.
The flagship M97 chip is designed for high-end autonomous driving and integrated cockpit-driving platforms. It is equipped with 16 Arm Cortex-A78AE CPU cores delivering 400KDMIPS and provides 720TOPS of AI computing power. The integrated ISP supports up to 16 cameras with a throughput of 4.5G Pixels/s, while the memory bandwidth reaches 460GB/s.
The mainstream M95 model is optimized for end-to-end autonomous driving solutions. It features 10 Arm Cortex-A78AE CPU cores with 257KDMIPS performance and offers 360TOPS of AI computing power. The ISP supports 14 camera inputs with a throughput of 2.6G Pixels/s, and the memory bandwidth is 260GB/s. Both chips feature a 70% reduction in ISP path latency compared to previous standards.
