In the second half of 2027, NVIDIA will launch the Rubin Ultra accelerator in a Kyber NVL576 configuration, featuring 144 accelerators per rack and 1 TB of HBM4e memory. The rack power consumption will reach 600 kW, compared to 40 kW for Hopper-based racks. The NVLink 6 interconnect will provide 3.6 TB/s per accelerator.
AMD plans to release the Instinct MI500 flagship accelerator in 2027, built on the 2nm CDNA 6 architecture with HBM4e memory. The company also announced the MI430X for HPC and the Helios 500 rack solution, which integrates MI500 accelerators with Verano CPUs and Pensando networking chips.
The EPYC Venice CPU lineup will expand in 2027 with the Venice-X and Verano models. Intel is preparing its Diamond Rapids Xeon 7 processors, manufactured on the 18A-P process at Intel Foundry. Both companies are adopting PCIe 6.0 as a standard to support high-speed data transfer between CPUs and GPUs.
CXL 3.0/3.1 technology will see widespread commercial adoption in 2027, enabling memory pooling and offloading KV-cache for AI inference. Penguin Solutions has already introduced a CXL-based server for KV-cache, reporting a 75% increase in GPU utilization and a twofold improvement in inference throughput.
The industry is moving toward Co-Packaged Optics (CPO) to reduce power consumption on 800 Gbps ports from 15-16 W to 6 W. Additionally, the UALink 1.0 standard, supported by a consortium of IT leaders, aims to enable the integration of up to 1024 accelerators from different vendors in a single cluster.
