Samsung Electronics has updated its roadmap for advanced memory technologies, focusing on the development of its first sub-10nm DRAM generation. The company is currently working on two parallel nodes for this class of memory, with the new B1b node utilizing a hybrid bonding structure.
The new D0a node will manufacture memory arrays and peripheral circuits on separate wafers. These components will then be integrated using a wafer-to-wafer bonding process. This method allows for independent optimization of both the array and peripheral device performance.
This hybrid bonding technology is already widely used in 3D NAND production. Compared to the 4F squared vertical channel transistor (VCT) approach, which requires high-aspect-ratio etching, the hybrid bonding process is already validated for mass production, lowering the commercialization threshold for new DRAM.
