Huawei is launching its Mate 90 smartphones this week, featuring new-generation Kirin processors. These chips utilize a 'tau scaling' layout method, which increases transistor density by 55% without requiring a transition to smaller process nodes.
The new architecture stacks planar structures into two layers, connected by vertical channels. In the Kirin 2026 chip, there are approximately 50 million such vertical interconnects with a 1.5-micrometer pitch, of which 10% to 15% are used for signal transmission.
By prioritizing energy efficiency over clock speed, the chip achieved significant power reductions: 66% for the NPU, 58% for the GPU, and 41% for the CPU. The NPU delivers 29 TOPS at a 63% lower frequency and a voltage reduced from 0.85 V to 0.55 V.
The design reduces data travel distance by 20% to 70%, addressing the fact that data movement accounts for 80% of a SoC's total energy consumption. Energy flux density dropped by 73%, though thermal management remains a constraint for future performance gains.
Huawei is already testing Kirin 2027 samples with a 1-micrometer channel pitch and over 100 million interconnects. The company plans to further reduce the pitch to 720 nm and increase the count to over 200 million within the next three years.
