The project involves configuring an Artix-7 FPGA board with a USB3300 PHY to function as a self-powered USB device. The setup utilizes Vivado and Vitis 2024.1, incorporating a MicroBlaze processor with 128 KB of BRAM, an AXI USB2 Device core, and a Clocking Wizard to manage 50 MHz and 24 MHz frequencies.
The primary challenge was that the USB3300 PHY on the board lacked a physical connection to the VBUS line, causing the standard AXI USB2 Device core to remain inactive. To resolve this, the author modified the encrypted RTL of the core to introduce a SELF_POWERED parameter, which forces the core to ignore the missing VBUS signal from the PHY.
The modification required propagating the new parameter through the core's hierarchy using a custom Python script, hdl-param-propagate. Additionally, the author updated the XGUI Tcl script and the component.xml file to expose the parameter in the IP Integrator interface and ensure Vivado recognizes the updated core configuration.
The final implementation includes a wrapper module for pin assignments and specific timing constraints for the 60 MHz ULPI clock. The entire project is automated via a Tcl script that handles IP versioning, parameter application, and the full build process, including synthesis and bitstream generation.
