Efficient Computer has introduced the Electron E1, a spatial dataflow processor designed for high energy efficiency in embedded systems. The architecture minimizes data movement between the processor and memory, which is a primary source of energy consumption in traditional von Neumann systems.
The E1 processor utilizes a grid of processing tiles connected via a programmable fabric. Unlike other dataflow chips, it supports arbitrary recursion and loops, allowing it to function as a general-purpose CPU. The company claims the E1 is 10 to 100 times more efficient than ARM-based processors for specific tasks like Fourier transforms and neural network convolutions.
Developers can test the E1 architecture through the Compiler Playground, which uses the proprietary effcc compiler to map C and C++ code onto the chip's spatial layout. The company is currently providing an Evaluation Kit to participants in its Early Access Program for real-world hardware testing.
The industry is increasingly shifting toward memory-first architectures to address the bottleneck of data transfer in AI workloads. Other startups, such as Positron, are also developing new processors, with Positron recently raising $875 million at a valuation of $5 billion for its Asimov chip.
