D-Matrix is integrating its next-generation Raptor XPUs into NVIDIA's NVLink Fusion interconnect. This partnership allows the startup to utilize NVIDIA's sixth-generation NVLink fabric and MGX reference architecture for rack-scale AI inference.
The integration supports configurations with up to 144 Raptor accelerators in a single domain. The system provides 3 TB/s of bandwidth per XPU and reduces XPU-to-XPU latency by 3x compared to standard Ethernet connections.
The company expects to complete the final design of Raptor chips by the end of 2026. Initial systems based on this architecture are projected for 2027, with the first units arriving in Q4 of that year.
D-Matrix previously shipped its Corsair XPU in November 2024. Following a funding round of $450 million, the company reached a valuation of $2 billion. D-Matrix is also working with Astera Labs on connectivity solutions.
