CXMT is utilizing a 16nm process and an 8-layer vertical stacking architecture for its HBM3 chips. Due to the absence of EUV lithography systems, the company relies on DUV multi-patterning schemes, which increases defect rates and packaging stress control difficulties.
The company's overall yield for these HBM3 memory grains is reported to be between 25% and 30%. When including strict final packaging and performance evaluation stages, nearly 80% of the chips fail the final inspection, resulting in an actual commercial delivery rate of approximately 20%.
This contrasts with global leaders SK Hynix, Samsung Electronics, and Micron Technology, whose HBM3 and HBM3E yields have stabilized at _60% or higher. CXMT's current low yield significantly hinders its ability to deliver large-scale batches to domestic AI chip customers such as Huawei Ascend, Cambricon, and Alibaba T-Head.
Despite these challenges, CXMT aims to improve its overall yield to an economically viable break-even point by the planned mass production cycle of late 2026 to 2027. The company is focusing on optimizing thermal compression packaging processes and collaborating with local packaging and testing giants.
