The Chinese Academy of Sciences has introduced a new gate-all-around (GAA) transistor architecture. This design achieved an on/off ratio exceeding 500,000 using existing DUV lithography equipment, theoretically enabling performance levels equivalent to 3 nm processes.
Unlike traditional FinFET technology, the GAA structure provides superior current control and reduces leakage. By increasing the spacing between transistors, the new architecture maintains necessary performance characteristics, allowing for the creation of 3 nm equivalents without the need for EUV lithography.
This development currently addresses limitations at the front-end-of-line (FEOL) stage, which involves the formation of the transistors themselves. However, the research does not represent a ready-to-use 3 nm manufacturing process.
Significant challenges remain for the subsequent stages of chip fabrication, specifically middle-end-of-line (MEOL) and back-end-of-line (BEOL) processes. These include the development of metal interconnects and the routing of the M0 layer, which must be resolved for full-scale industrial production.
