Micron Technology has announced its next-generation G11 3D NAND flash memory, skipping the G10 designation. The new architecture features over 400 layers, marking a significant increase from the 276 layers found in the current G9 generation used in products like the Crucial P510 SSD.
The company achieved a twofold increase in bit density compared to G9 by utilizing a new manufacturing process and reducing cell pitch. While Micron has not confirmed the exact bit-per-square-millimeter metrics for TLC or QLC configurations, estimates suggest a density of approximately 42 gigabits per square millimeter.
To enhance performance, Micron is adopting a wafer-on-wafer bonding technique, separating the memory array from the I/O logic during production. This approach aligns the company with industry practices already utilized by manufacturers such as Samsung, Kioxia, SanDisk, and YMTC.
The G11 architecture also improves data transfer speeds between the controller and NAND by 50 percent, rising from 3.6 gigabits per second to approximately 5.4 gigabits per second. Additionally, the energy efficiency of the new memory is expected to improve, with power consumption per bit dropping by more than 25 percent.
Micron has scheduled the transition to mass production for the G11 flash memory for the second half of 2027.
