Huawei has officially introduced its Kirin 9050 series, which the company describes as its first logic-folding tau-chip. The processor features a new generation of the Da Vinci architecture NPU, designed to run 30B MoE large language models directly on the device without requiring cloud connectivity.
The updated NPU architecture delivers a 140 percent performance increase while reducing power consumption by 66 percent. It incorporates a Transformer engine, an ultra-low power sensing engine, and the CANN heterogeneous computing architecture to support multi-level memory and compute optimization.
The new NPU enables several on-device features, including AI screen reading, Xmage 2.0 smart photography, AI eye-tracking for page turning, and an updated off-screen map function. These capabilities leverage the chip's ability to process complex tasks locally.
During a media briefing held in October 2026, Xu Songyu, head of the wireless terminal chip product management department, stated that the Kirin 9050 series marks the start of a 10-year development cycle. Huawei aims to reach P-core frequencies exceeding 5GHz by 2031.
