The project focuses on building a framework to compare greedy instruction scheduling heuristics with optimal results for VLIW architectures, specifically targeting the Elbrus e2k-v6 processor. The developer created a model based on measurements from the lcc-1.29.16 compiler, including port matrices, operation latency, and device occupancy.
Initial experiments used a Qwen2.5-3B-Instruct model with QLoRA to predict instruction schedules. The AI model proved slower and less reliable than the greedy algorithm, taking approximately 30 seconds to generate a schedule compared to 3 milliseconds for the greedy heuristic, while often producing illegal instruction sequences.
To address these issues, the developer implemented a 'CAB' (Candidate-based) approach. This method uses the model to suggest an ordering of instructions while delegating the 'bookkeeping'—ensuring valid channel assignment and dependency handling—to a deterministic list scheduler. This hybrid approach improved performance on complex graphs.
The framework is designed as a modular monolith in Python 3.10, allowing users to swap scheduling strategies between heuristic, exact, and learned models. The developer is seeking access to physical e2k-v6 hardware to refine the model's assumptions regarding latency and inter-cluster communication, as current data is based on compiler behavior rather than hardware specifications.
