South Korean firm DeepX has finalized the DX-M2 AI accelerator, designed to run large language models with 20–100 billion parameters on edge devices. The chip maintains a 5-watt power envelope while delivering 80 TOPS of performance. Production samples are expected in March 2027, with mass production scheduled for autumn 2027.
The DX-M2 features a 2nm process and a memory bandwidth of 150 GB/s, triple that of its predecessor. DeepX is collaborating with Samsung to integrate LPDDR5x-PIM technology, which performs computations within the memory to reduce latency. Simulations suggest this could boost token generation speeds for Llama 3.1 8B models by 6.7 times, though it increases power consumption.
The accelerator supports MoE architectures, speculative decoding, and TurboQuant compression. DeepX is positioning the chip for robotics, automotive electronics, and AI PCs. The company offers a software platform called Newton, designed to allow developers to migrate from Nvidia Isaac by simply changing API names, with 17 compatible libraries already available.
DeepX has secured over 100 orders for its existing DX-M1 chip from manufacturers of drones, robots, and industrial equipment. The company is currently collaborating with Intel, AMD, and AWS to expand its ecosystem. Future plans include the 2028 launch of the DX-M3, which will feature a chiplet architecture and support for LPDDR6-PIM memory.
