The Chinese Academy of Sciences (CAS) has unveiled a new Gate-All-Around (GAA) transistor architecture designed for production using DUV lithography. This development aims to assist the domestic semiconductor industry in manufacturing advanced chips despite the ongoing restrictions on EUV scanner imports.
GAA transistors represent the next evolution after FinFET technology, featuring a gate that surrounds the conductive channel from all sides. This design improves current control, reduces leakage, and enhances energy efficiency as chip components shrink. The method relies on immersion lithography and multi-patterning techniques to extend the capabilities of older DUV systems.
Experts note that this architecture does not equate to achieving a full 3nm process node. Instead, it allows for performance improvements in specific parameters. A significant challenge remains in forming microscopic contacts and metal interconnects between billions of elements, which is notoriously difficult to achieve using DUV equipment.
The new design allows for increased spacing between transistor elements without significant performance degradation. This could eventually lead to reduced logic cell heights and higher transistor density. Meanwhile, companies like Huawei are exploring alternative methods, such as the LogicFolding technology, which utilizes vertical layering of silicon to boost computational density.
