The commercial success of a semiconductor plant depends on the annual production volume: tens of thousands of wafers for MEMS and photonics, or hundreds of thousands for CMOS. Each wafer contains from several dozen to several thousand chips, depending on the product type.
The complexity of the manufacturing process varies significantly. MEMS technology is relatively simple with a process route of up to 100 steps. In contrast, modern CMOS processes require approximately 2,000 operations, often developed through consortia like IMEC in Belgium, where leaders such as Intel, Samsung, TSMC, and Global Foundries collaborate.
Technological progress in CMOS has shifted from simple scaling down to the introduction of new materials and architectures. Since the 90 nm node, processes have integrated high-k materials like hafnium oxide, copper metallization, and germanium in channels, as well as 3D gates and strained channels to maintain performance.
For those starting production, there are two main paths: purchasing a ready-made technology from providers like IMEC or building it independently. Companies like Mikron (which bought 180 nm and 90 nm technologies from ST Microelectronics in 2006 and 2010) and Angstrem-T (which acquired 130 nm technology from AMD/Global Foundries in 2007) have used this approach.
Equipment selection is critical. Industrial-grade equipment is recommended over university-grade, as the latter is unreliable and lacks support. For limited budgets, refurbished industrial equipment from manufacturers like ASML, Lam Research, or Ichor is a viable option. Automation levels also impact yield and labor productivity.
The choice of wafer size is tied to the technology node. All CMOS technologies below 90 nm are developed for 300 mm wafers. Equipment for 200 mm wafers or smaller is significantly cheaper but cannot support processes below 90 nm. Specialized materials like A3B5 semiconductors or piezoelectrics may require smaller wafer sizes.