Remote FPGA Debugging on Zynq SoC via XVC

The article describes a method for debugging FPGA designs on Zynq SoC using the Integrated Logic Analyzer (ILA) without a physical JTAG connection. The approach relies on the Xilinx Virtual Cable (XVC) and the Debug Bridge IP core to enable communication via Ethernet.

The author notes that standard ILA insertion via Vivado's 'Set Up Debug' is not supported when using a Debug Bridge. Instead, the ILA must be added as an IP instance directly in the RTL or Block Design. The setup requires two Debug Bridge instances: one in 'From AXI to BSCAN' mode and another in 'From BSCAN to DebugHub' mode.

For the software side, the author details the creation of a device tree overlay using the classic DTG-flow with Vitis 2025.1. The process involves generating a plugin fragment (pl.dtsi) and compiling it into a .dtbo file, which allows the Linux kernel to interface with the debug bridge via the UIO driver.

The implementation was tested on a Zynq RK-7020F Rev 1.1 board. The author emphasizes that the Debug Bridge must be correctly configured to handle BSCAN master interfaces to avoid DRC errors during bitstream generation, and the clock source for the ILA must be stable during the Linux boot process.