Researchers at IonQ have developed a real-time quantum error correction decoding pipeline that operates on a single Apple M4 Max CPU. The system utilizes 12 of the 16 available cores to manage simulated workloads of up to 408 logical qubits, executing over 1 million T gates and 1.3 million logical measurements.
The study, published on August 25, 2026, demonstrates that the pipeline introduces a computational stretch of less than 0.3% at a physical error rate of 10^-4. Even when the error rate increases to 5x10^-4, the performance overhead remains below 12%. This marks the first instance of full-scale decoding on off-the-shelf hardware.
The architecture employs a dual-decoder design, separating continuous error correction from low-latency outcome decoding. This approach leverages the 1 to 5 millisecond syndrome extraction cycle times characteristic of trapped-ion quantum systems, which are slower than those found in superconducting qubit architectures.
The results serve as a proof of concept for the classical component of IonQ’s Walking Cat fault-tolerant architecture, which aims to scale to over 10,000 physical qubits. By utilizing consumer-grade chips instead of specialized FPGAs or ASICs, the company seeks to reduce the costs and supply chain dependencies associated with quantum system development.
