SemiAnalysis conducted a teardown of the Intel Panther Lake processor, confirming the implementation of RibbonFET transistors and the PowerVia power delivery system in a consumer product. RibbonFET uses four stacked horizontal silicon nanosheets, while PowerVia moves power infrastructure to the back of the die.
The analysis indicates that the Intel 18A process density is comparable to TSMC N3E. While 18A is approximately 18.6% denser than Intel 3, it does not surpass the density of newer TSMC N3P, N2, or Samsung SF2 nodes. The 18A and N3E designations are marketing terms rather than physical measurements.
Panther Lake utilizes a chiplet architecture with Foveros-S packaging. The compute die is manufactured on Intel 18A, while the 12-core Xe3 graphics die is produced by TSMC using N3E. The I/O die is manufactured by TSMC on the N6 process, and the 4-core Xe3 variant is produced on Intel 3.
Architectural updates include the Cougar Cove performance core, which features a 3 MB L2 cache per core, a 20% increase over the previous generation. The NPU 5 in Panther Lake is 36.9% smaller than the NPU 4 in Lunar Lake while maintaining INT8 performance and adding FP8 support.
The study highlights that Intel's GPU core size varies significantly by process. A single Xe3 core on Intel 3 is 55% larger than a core on the TSMC N3E-based die. This suggests that while Intel can manufacture its own GPUs, TSMC's N3E allows for higher density of graphics compute blocks.
