The project focuses on implementing a video processing pipeline on the Zynq-7020 FPGA, capturing data from an OV5647 sensor via MIPI-CSI-2 and outputting it through HDMI and Ethernet UDP. The development involves transitioning from a vendor-provided bitstream to a custom design, addressing challenges such as input delays, memory configuration, and color component alignment.
The custom bitstream achieves a stable 1080p30 video output with approximately 30.8 frames per second. Without the JPEG encoder, the design utilizes 26.6% of logic tables, 20.8% of registers, 25.4% of block RAM, and 3.6% of multipliers. The system architecture includes a receiver, a pixel-to-display synchronizer, and a serializer for HDMI output.
Initial testing revealed issues with image noise and checksum errors, traced to incorrect input delay calibration in the receiver. By setting the calibration to a fixed mode with tap 5, the receiver achieved error-free operation. The project emphasizes that 'live' video does not guarantee a correct design, as minor timing misalignments can cause intermittent data corruption.
The author utilized a standardized set of scripts and vendor-compatible memory addresses to compare the custom design against the vendor's original bitstream. This methodology allowed for the identification of hidden parameters, such as the necessity of enabling the calibration block, which prevents implementation errors during the design phase.
Further diagnostics involved testing color filter phases and gamma table configurations to isolate image artifacts. By setting the gamma table to a uniform value, the team verified the pipeline's integrity. The final system supports MJPEG transmission over HTTP with potential repacking into RTP/UDP, achieving a network stream performance of 23 frames per second.
