The new Kirin 9050 Pro chip is the first to implement logic folding technology, which arranges logic units in layers within a single chip. This architectural shift from a flat layout to a 3D structure reduces signal transmission paths and lowers latency, resulting in higher overall performance.
Huawei's chief semiconductor scientist, Liao Heng, explained that the high-density vertical interconnects between two bare chip layers are key. In the Kirin 2026 chip, for example, there are approximately 50 million connections, with 5 to 10 million dedicated to signal communication, significantly exceeding the same metric for standard 3D packaging, which typically has tens or hundreds of thousands of connections.
Experts suggest that this 3D circuit architecture allows for faster signal transmission and innovation through 'time miniaturization.' This approach provides a new path forward as traditional chip miniaturization under Moore's Law reaches physical limits at the few-nanometer process level.
The technology is likely to be expanded beyond smartphones to personal computers and servers. This transition may require changes in thermal materials, battery materials, and further iterations of the HarmonyOS ecosystem and AI applications.
