Chinese manufacturer CXMT has introduced its fifth-generation DRAM process technology, designated as G5. The company utilizes quadruple-patterning lithography to achieve an active-area half-pitch of 11.95nm. Additionally, the process incorporates a high-K metal gate (HKMG) technique that reduces the core cell array height to 6,762nm.
The new manufacturing process enables storage capacitors with a depth-to-width aspect ratio of approximately 45:1. This design modification allows for a reduction in DRAM cell area, facilitating the placement of more memory arrays on a single wafer. CXMT claims this technology increases the number of gross dies per wafer by at least 50% compared to its previous G4 generation.
The first mass-produced components utilizing the G5 process are 24Gb LPDDR5X memory chips. These devices provide 50% higher capacity than the company's prior comparable products and are currently being integrated into flagship smartphones within the Chinese market. The chips are manufactured in two distinct package formats.
Despite these developments, the company has not disclosed specific manufacturing yields or cost-per-bit metrics. Industry experts note that the 11.95nm figure refers specifically to the active-area half-pitch rather than a standard process-node designation. Consequently, the G5 technology does not necessarily imply parity with the latest DRAM processes from industry leaders like Micron, Samsung, or SK hynix.
