A researcher required a 160 GiB array for a scientific task, necessitating high-speed random access and rapid memory allocation. The project utilized a dedicated server equipped with an AMD EPYC 7713 processor, featuring 64 physical cores, 128 logical cores, and 256 GB of DDR4-3200 RAM.
The study compared standard 4 KiB memory pages with 1 GiB Huge Pages. Using standard pages for a 160 GiB array resulted in over 42 million page faults during the initial access, adding approximately 69 seconds to the processing time. The researcher noted that the operating system kernel must manage these millions of pages, which impacts performance.
To optimize memory usage, the researcher implemented dense packing of 5-byte elements, reducing the required space from 256 GiB to 160 GiB. The tests confirmed that Go slices do not create a performance bottleneck compared to raw mmap pointers, as the overhead is primarily tied to kernel-level page allocation.
Multithreaded testing showed significant performance gains. By dividing the array into 120 segments and using separate goroutines, the initial filling time dropped from 261.49 seconds in a single-threaded scenario to 7.15 seconds. The researcher concluded that Huge Pages are essential for reducing TLB misses during random access.
