The FlagChip FC7300F8MDT microcontroller features three ARM Cortex-M7 processor cores. The architecture requires each core to operate with its own vector table, stack pointer, reset handler, main function, heap, and stack, while sharing peripheral registers and global variables.
Core0 is the primary core that initiates the startup of Core1 and Core2. Attempting to trigger Core2 from Core1 results in a HardFault_Handler error. Developers can verify the validity of the vector tables in the on-chip NOR Flash memory before initiating the secondary cores.
Inter-core communication is managed via a dedicated MailBox subsystem. This hardware component handles data transfer between cores using a single global instance of a handle structure. Data must be stored in global memory to ensure successful transmission, as stack-allocated data may lead to corruption.
The SDK provides specific attributes to place code for each core into distinct Flash memory segments. Resetting a specific core involves calling its reset handler, though global variables in RAM retain their values, requiring re-initialization of software components upon restart.
