Intel introduced the 8087 math coprocessor in 1980, which accelerated floating-point operations by up to 100 times. The chip utilized a stack-based architecture with eight registers and two temporary registers, each 80 bits wide. Its internal operations were governed by 1648 microinstructions stored in a dedicated ROM, with each microinstruction being 16 bits long.
The FXCH instruction, designed to swap two floating-point registers, requires 14 microinstructions to execute. The process involves reading values from the stack into temporary registers tmpA and tmpB, checking for empty tags, and handling potential invalid operation exceptions. If a register is empty, the system can replace the value with a Not a Number (NaN) constant.
The 8087 chip architecture features two distinct data paths: a 16-bit path for exponents and signs, and a 64-bit path for significands. Each register includes two tag bits to identify the data type, such as valid, zero, special, or empty. These tags are critical for the coprocessor to manage operations and detect errors, such as invalid operations or stack underflows.
The coprocessor implements six categories of exceptions, including division by zero, overflow, underflow, and precision loss. Developers can configure the chip to either trigger a CPU interrupt or mask these exceptions to continue calculations. The microcode includes specific nop instructions, likely to accommodate timing constraints of the hardware registers or as remnants of development.
