Arm has introduced the Neoverse CSS N4 Ranger platform, a semi-custom compute subsystem designed for data center applications. The platform supports between 8 and 128 Neoverse N4 cores per die, with clock speeds reaching up to 3.8 GHz. It is built on the TSMC N3P process and utilizes UCIe for chip-to-chip interconnects, supporting multi-chiplet and multi-socket designs.
The new platform features significant memory and cache upgrades. It supports either DDR5 or LPDDR6 memory and provides up to 256 MB of L3 cache per die. Each core is equipped with 2 MB of L2 cache, 64 KB of L1 instruction cache, and 64 KB of L1 data cache. For I/O, the system supports up to 128 lanes of PCIe 7/6 and CXL 4.0.
Compared to the previous Neoverse CSS N2 platform, the N4 Ranger offers a substantial increase in capacity. While the N2 topped out at 64 cores and 64 MB of L3 cache, the N4 doubles the core count and quadruples the L3 cache. Arm claims that with 128 cores at 3 GHz and 2 MB of L2 cache per core, the platform delivers twice the socket performance of Neoverse N3, 1.25x the performance per watt, and 1.75x the memory bandwidth.
Alongside the Neoverse CSS N4, Arm revealed that Oracle and ByteDance will deploy its AGI chip, joining Meta, Lenovo, SAP, OpenAI, and Cloudflare. The AGI chip is a dual-die CPU with up to 136 Neoverse V3 cores, up to 272 MB of L3 cache, and clock speeds up to 3.7 GHz. It is built on a 3nm node and supports up to 6 TB of memory capacity per chip running at DDR5-8800, achieving sub-100ns memory latency by integrating memory and I/O on the same die as compute.
