Arm has introduced the Neoverse CSS N4 Ranger compute subsystem, a platform designed to help companies develop custom server processors without starting from scratch. The platform allows for the configuration of core counts, cache sizes, and I/O components based on specific requirements.
The Neoverse CSS N4 supports between eight and 128 Neoverse N4 cores with clock speeds reaching 3.8 GHz. The architecture supports multi-chiplet or multi-socket configurations using UCIe interconnects. Chips based on this platform are intended for production using the TSMC N3P manufacturing process.
Technical specifications include support for DDR5 or LPDDR6 memory, up to 256 MB of L3 cache per die, and up to 128 lanes of PCIe 6.0/7.0 and CXL 4.0. Each core features 64 KB of L1 cache for instructions and data, along with up to 2 MB of L2 cache.
Arm claims that a 128-core Neoverse CSS N4 configuration at 3 GHz provides double the performance per socket compared to the Neoverse N3. It also offers a 1.25x improvement in performance per watt and a 1.75x increase in memory bandwidth.
Additionally, Arm detailed new deployments of its AGI processor, which utilizes Neoverse V3 cores. These chips are being integrated into infrastructure by Oracle and ByteDance, joining previous adopters such as SAP, OpenAI, and Cloudflare.
