AMD CEO Lisa Su introduced the next-generation EPYC Verano processor at the 2026 Open Compute Project Global Summit. The company confirmed that Verano is slated for a 2027 release and will serve as a host processor for AI server nodes, focusing on data scheduling and supporting GPU accelerators.
The processor marks the first EPYC line to feature an LPDDR memory interface. While reports suggest the use of LPDDR5X and SOCAMM2 modules for increased bandwidth and capacity in compact rack spaces, AMD has not yet finalized the specific memory type, capacity, channel count, or speed configurations.
Regarding core counts, conflicting information persists. While early technical previews pointed to a maximum of 72 cores and 144 threads, recent discussions of 192 cores remain unverified. AMD has not clarified if this figure refers to a single chip, a dual-socket system, or a total rack configuration.
The architecture is expected to utilize TSMC 2nm process technology. Based on visual analysis of the hardware, it may feature eight compute chiplets, two large I/O chiplets, and four LPDDR5X controllers, though AMD has not officially confirmed the chiplet layout or the use of standard Zen 6 cores.
Verano is designed to work in tandem with Instinct accelerators within rack-scale AI systems. The primary development goals are optimizing system-level energy efficiency and improving CPU-to-GPU interconnects, rather than maximizing general-purpose core density.
